With Moore's Law looking more like a fairy tale, GPU and data centre chip makers are being forced to slap together more silicon to handle AI’s ever-growing demands. The problem is, a single slice of silicon tops out at around 800 mm2 unless it ends up in a government lab. So Chipzilla is now banging on about how to stitch loads of these dies together like a Frankenstein monster using fancy packaging.
At the event, Chipzilla rolled out three bits of wizardry designed to stretch how much silicon can be packed into one place. These include new tricks for hooking dies together, improved glue for attaching dies to the package, and a better heat remover that doesn’t buckle under the strain. Intel has come up with packages that can hold more than 10,000 mm2 of silicon inside a footprint bigger than 21,000 mm2. That’s roughly four and a half credit cards of pure heat.
One bottleneck has been how to get all these silicon bits to talk to each other through the packaging. Organic polymer substrates are cheap and cheerful but can’t handle dense wiring. Silicon substrates are better, but cost more.
Chipzilla's original trick, dubbed EMIB, plonked a skinny slice of silicon in the organic package to connect the edges of dies. This sliver came etched with tight interconnects that gave more bandwidth without going full silicon-substrate.
At the conference, Chipzilla is wheeling out EMIB-T, which adds vertical copper connections known as through-silicon vias (TSVs). These let power zip straight up to the chips from the circuit board below instead of meandering round the EMIB. EMIB-T has a copper grid acting as a ground plane to quieten down the power noise.
Intel vice president of substrate packaging technology Rahul Manepalli told the gathered throngs that while the whole thing sounded simple "It is a technology that brings a lot of capability to us.” With EMIB-T and pals, customers can now squeeze in silicon the size of 12 full dies using at least 38 of these interconnect bridges.
Keeping all these dies in place without melting things is another problem. Today’s thermal compression bonding involves solder bumps and heat, but the different rates of expansion between silicon and substrates make it tricky to keep everything aligned.
Chipzilla's new low-thermal-gradient thermal compression bonding is meant to make this expansion mess more manageable, so engineers can go bigger without everything popping off. It also lets them crank up the connection density to one bump every 25 microns.
More silicon means more heat, so Intel had to rework the metal heat spreader too. The old ones would warp or miss the hot dies completely, making heat transfer unreliable.
Chipzilla's answer was to build the heat spreader in sections and reinforce it to keep it flat under pressure.
“Keeping it flat at higher temperatures is a big benefit for reliability and yield,” Manepalli said.
